1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly a charge pump circuit for generating a positive or negative voltage on the basis of a power supply potential supplied from an external source, and an operation method of a non-volatile memory using the charge pump circuit.
2. Description of the Prior Art
A power supply supplied from an external source to a semiconductor integrated circuit is typically provided with a simple power supply or two power supplies. However, an electric device such as flash memory which needs a plurality of power supplies requires to generate internally a desirable voltage. A circuit playing such a role is called xe2x80x9ccharge pump circuitxe2x80x9d. The charge pump circuit is comprised of a plurality of capacitors, drivers, and oscillators, and cannot help scaling down the dimension of the power supply voltage to perform a reduced power consumption with development of semiconductor integrated circuits in recent years. Therefor, a charge-up from a low voltage is requisite, which directs to increase the stage number of capacitors and drivers. As the miniaturization of a memory array section advances, it is difficult to miniaturize a power supply unit such as charge pump in the actual state.
FIG. 16 is a circuit diagram showing a conventional charge pump circuit for positive voltage generation, for example, as described in JP-A2000-49299. This is a circuit which generates a positive voltage higher than an external power supply. In the drawing, reference numerals 41 and 42 each designate an inverter, which constitutes a driver 104; 51-53 each designate a diode; 61-63 each designate a capacitor; 71 designates a capacitive load provided by an internal circuit, wire resistance, and so on; 101 designates an external power supply which feeds Vdd potential; 102 designates a ground which feeds GND potential; 105 designates an oscillator; 108 designates an NMOS transistor (N-channel MOS transistor); and N1-N4, N11, and N12 each denote a node.
Here, the external power supply 101 is a power supply to be applied so that a user can utilize a semiconductor integrated circuit. In addition, the diodes 51-53, capacitors 61-63, and drivers 104 are components which are necessary for the charge pump circuit for positive voltage generation; and the oscillator 105 is a circuit which generates a pulse-form input signal necessary to operate the charge pump circuit for positive voltage generation.
The input signal generated from the oscillator 105 is input to the inverter 41 constituting the driver 104 as a clock signal "PHgr" to be inverted, thereby resulting in a clock signal /"PHgr". This branches at the node N11 into two signals in which the one signal affects the capacitor 62 and the other signal is input to the next inverter 42 to be inverted, resulting in the reverted clock signal "PHgr". This affects the capacitors 61 and 63 via the node N12.
In addition, the NMOS transistor 108 which connects to the external power supply 101 charges the capacitors 61-63 and capacitive load, and serves as a transistor which prevents the electric charge boosted to a positive voltage from flowing into the ground 102. The capacitive load 71 is comprised of decoders, wells, and the like of a non-volatile memory array, and is a capacitance to be charged by the charge pump circuit. Note that NVth represents a threshold voltage value of the NMOS transistor 108, while Vth represents a threshold voltage value of each of the diodes 51-53.
The operation will be next described below.
The initial status of the charge pump circuit for positive voltage generation is denoted in FIG. 17. Here, H level (Enable Signal or ES) to the gate of the NMOS transistor 108 is input to be active state, i.e. ON state, and an electric charge of Vddxe2x88x92(NVth+3Vth) is charged in the capacitive load 71. As shown in FIG. 18, in the charge-up status, an input signal (INPUT) generated from the oscillator 105 with respect to the aforementioned initial status is input to the driver 104, the complimentary clock signals "PHgr" and /"PHgr" which are generated via the inverters 41 and 42 constituting the driver 104 are applied alternately to the capacitors 61-63, which are pumped up based on the characteristics of the diodes. In such a way, the output POUT may be booted up to 3Vddxe2x88x92(NVth+3Vth) at the maximum.
On the other hand, FIG. 19 is a circuit diagram showing a conventional charge pump circuit for negative voltage generation, which generates a negative voltage of a larger dimension than that of the external power supply 101. In the drawing, reference numeral 113 designates a PMOS transistor (P-channel MOS transistor); the other components are similar to those of FIG. 18, and these redundant description will be omitted. The PMOS transistor 113 fills an electric charge to the capacitors 61-63 and capacitive load 71, while it serves as a transistor in which an electric charge leveled down to a certain negative voltage prevents from flowing into the ground 102 of an external power supply. Note that PVth denotes a threshold voltage value of the PMOS transistor 113.
In this case, a difference between the charge pump circuits for positive voltage generation and for negative voltage generation is simply in that the polarity of the electric charges to be charged in the capacities 61-63 and 71 is contrary; the operation detail from the initial status to the charge-up status is the same, and the description will be omitted. In the charge pump circuit for negative voltage generation, the output NOUT may be leveled down upto a voltage of xe2x88x923Vdd+(PVth+3Vth) at the maximum.
Then, FIGS. 20 and 21 are circuit diagrams showing a conventional charge pump circuit, for example, disclosed in JP-A 07/177729; FIG. 20 represents a positive voltage output status, while FIG. 21 represents a negative voltage output status. A problem will be described below when both positive and negative voltages are generated by a simple charge pump circuit. In the drawings, reference numeral 64 designates a capacitor; 109 designates a PMOS transistor; and the other components are similar to those of the circuits of FIGS. 18 and 19 above.
A difference between such a charge pump circuit and the above-described charge pump circuit which can generate only either of positive and negative voltages is as follows: The ground 102 is connected to the node N4 by way of the PMOS transistor 109, and the capacitor 64 is prepared instead of the capacitive load 71, whereby the input signal generated from the oscillator 105 via the driver 104 is provided as clock signals "PHgr" and /"PHgr".
The operation will be next described below.
Referring to FIG. 20, for the purpose of generating a positive voltage, when H level is input to the gate of the NMOS transistor 108 and H level is input to the gate of the PMOS transistor 109, the NMOS transistor 108 is ON state, while the PMOS transistor 109 is OFF state. Thus, since the charge pump circuit is equivalent to that shown in FIG. 16, when the complimentary clock signals "PHgr" and /"PHgr" (Vdd potential) are input to the capacitors 61-64 via the inverters 41 and 42 constituting the driver 104, the potentials of the nodes N1-N4 are leveled up and down in synchronization with the clock signals "PHgr" and /"PHgr" in pulse form, and the capacitors 61-64 are pumped up, coupled with the characteristics of the diodes 51-53, thereby providing a positive voltage output POUT.
On the other hand, referring to FIG. 21, for the purpose of generating a negative voltage, when L level is input to the gate of the NMOS transistor 108 and L level is input to the gate of the PMOS transistor 109, the NMOS transistor 108 is OFF state, while the PMOS transistor 109 is ON state. In such a way, since the charge pump circuit is equivalent to that of FIG. 19, similarly, the capacitors 61-64 are pumped up, thereby providing a negative voltage output NOUT.
Since the conventional charge pump circuit is configured as described above, there are the following problems.
On generating the positive voltage of FIG. 20, as described in above, the NMOS transistor 108 is set to ON state so as to charge a Vddxe2x88x92Vth potential, while the PMOS transistor 109 is OFF state (Vdd potential) so as not to discharge an electric charge toward the ground 102. However, the positive voltage output POUT is set to Vdd potential or more, resulting in discharging from the PMOS transistor 109 to the ground 102 and therefor has no boosted potential, thereby obtaining no desired positive high voltage output.
In addition, on generating a negative voltage of FIG. 21, the PMOS transistor 109 is ON state so as to charge a (GND+Vth) potential, and the NMOS transistor 108 is put on OFF state (GND potential) so as to prevent charging from a power supply 101. The negative voltage output NOUT, however, is brought to GND potential or less, so that Vdd potential may be charged from the power supply 101 by way of the NMOS transistor 108, thus not falling the potential. As a result, a negative high voltage output cannot be also obtained.
As described above, there is a problem that the conventional charge pump circuit for positive and negative voltages generation can generate the two power supplies of positive and negative voltages, while a desired high voltage output cannot be obtained.
In addition, when a non-volatile memory such as flash memory is operated by use of such a charge pump circuit, it is necessary to carry out injections and extractions of electrons by applying opposite high voltages to the floating gate and the well, respectively. However, in an operation method of a non-volatile memory using a charge pump circuit capable of generating both positive and negative voltages, there is a problem that the method cannot apply simultaneously the positive and negative voltages to word lines and wells.
The present invention has been made to solve the aforementioned problems, and it is an object to obtain a charge pump circuit which enables two power generations of positive and negative voltages on a desired large dimension, and an operation method of a non-volatile memory using the same.
According to a first aspect of the present invention, there is provided a charge pump circuit comprising: a first power supply node for receiving a first power supply potential; a first reverse current prevention means connected between the first power supply node and a first internal node; a first output node, connected to the first internal node, for outputting a first output potential; a second power supply node for receiving a second power supply potential lower than the first power supply potential; a second reverse current prevention means connected between the second power supply node and a second internal node; a second output node, connected to the second internal node, for outputting a second output potential; and power supply generation means, connected between the first internal node and second internal node, for enhancing the potential of the second internal node as compared to that of the first internal node, wherein the power supply generation means is formed on or within a semiconductor substrate, and includes a diode element provided so as to flow a current from the first internal node to the second internal node, and a capacitor having one electrode connected to the first and second nodes, and the other electrode provided with a clock signal.
Here, a plurality of the diode elements may be connected in series, and further comprise a capacitor having one electrode connected to a connection node in which these diode elements are connected to each other, and the other electrode provided with a clock signal.
The first reverse current prevention means may be constructed such that a diode element and a P-channel MOS transistor is connected in series to each other from the side of the first power supply potential, and the second reverse current prevention means may also be constructed such that a diode element and an N-channel MOS transistor is connected in series to each other from the side of the second power supply potential.
A first switching circuit may also be connected between the diode element and the P-channel MOS transistor of the first reverse current prevention means and a second switching circuit may also be connected between the diode element and the P-channel MOS transistor of the second reverse current prevention means.
A first switching means may be provided between the output of said first reverse current prevention means and the first internal node, and a second switching means may be provided between said output and the connection node, and a third switching means may be provided to the other electrode of the capacitor connected to the first internal node.
The diode element may be composed of a poly-diode or well-diode.
Specifically, the well-diode includes a bottom N-well formed in the P-type semiconductor substrate, a P-well formed in said bottom N-well, and a N-well formed in said P-well, and an N-channel MOS transistor of which the source is connected to ground and the drain is connected to said bottom N-well.
According to a second aspect of the present invention, there is provided an operation method of a non-volatile memory using a charge pump circuit comprising: a first power supply node for receiving a first power supply potential; a first reverse current prevention means connected between the first power supply node and a first internal node; a first output node, connected to the first internal node, for outputting a first output potential; a second power supply node for receiving a second power supply potential lower than the first power supply potential; a second reverse current prevention means connected between the second power supply node and a second internal node; a second output node, connected to the second internal node, for outputting a second output potential; and power supply generation means, connected between the first internal node and the second internal node, for enhancing the potential of the second internal node as compared to that of the first internal node, wherein the power supply generation means is formed on or within a semiconductor substrate, and includes a diode element provided so as to flow a current from the first internal node to the second internal node, and a capacitor having one electrode connected to the first and second nodes, and the other electrode provided with a clock signal, the non-volatile memory having a control gate which is connected to a word line for implementing a storing operation and an erasing operation, and a floating gate as a storage element, on a well formed inside the substrate via a dielectric, whereby a positive voltage and a negative voltage supplied from the charge pump circuit are applied to the word line and well for a certain period of time alternately.
Here, a minimum electric charge may be supplied to the word line and the well to maintain a predetermined potential between the word line and the well.